1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit that outputs a variable duty and/or variable frequency clock signal, and to a semiconductor integrated circuit including the PLL circuit.
2. Description of Related Art
FIG. 13 is a block diagram showing a configuration of an LSI (Large Scale Integration) including a conventional PLL circuit. In FIG. 13, the reference numeral 1 designates a phase comparator that compares the phase of a reference clock signal CLK with an internal clock signal of the LSI, and outputs pulses with a width corresponding to the phase difference; and 2 designates a charge pump circuit for converting to a voltage the pulses supplied from the phase comparator 1.
The reference numeral 3 designates a VCO (Voltage Controlled Oscillator) that generates a clock signal with a frequency corresponding to the voltage supplied from the charge pump circuit 2; 4 designates an output driver circuit for supplying internal components of the LSI with a clock signal 116 fed from the VCO 3; and 5 designates a circuit block consisting of flip-flop circuits 6. The output driver circuit 4, receiving the clock signal 116 from the VCO 3, reduces the output impedance to increase its current drive capacity for driving the load consisting of the flip-flop circuits 6. The reference numeral 7 designates a PLL circuit comprising the phase comparator 1, charge pump circuit 2, VCO 3 and output driver circuit 4.
Next, the operation of the conventional LSI will be described.
The phase comparator 1 receives at an input terminal R the reference clock signal CLK fed from the outside of the LSI via an input buffer circuit (not shown), and at an input terminal V the internal clock signal 116 fed back from the output driver circuit 4. The phase comparator 1 compares the phases of the two inputs, and outputs pulses with a width corresponding to their phase difference: If the phase of the clock signal 116 lags behind that of the reference clock signal CLK, the pulses are output from an output terminal U; whereas if the phase of the clock signal 116 leads that of the reference clock signal CLK, the pulses are output from an output terminal D.
The charge pump circuit 2, receiving the pulses fed from the output terminal U or D of the phase comparator 1, converts the pulses into a voltage, and outputs it from the output terminal Vout. Receiving the voltage from the charge pump circuit 2 at its input terminal Vin, the VCO 3 outputs from its output terminal Fout the clock signal 116 with an oscillation frequency corresponding to the voltage. Thus, the clock signal 116 comes to resemble the reference clock signal CLK, the PLL circuit 7 locks after repeating such loops, and the clock signal 116 matches the reference clock signal CLK closely.
FIG. 14 is a block diagram showing the structure of the VCO 3 in FIG. 13. In FIG. 14, reference numerals 11, 12, 13, 14 and 15 each designate a CMOS (Complementary Metal Oxide Semiconductor) inverter (INV); 16 designates an input side control circuit for carrying out control in response to the voltage supplied to the input terminal Vin; 17 designates a power supply side control circuit for carrying out control in accordance with a command from the control circuit 16; 18 designates a ground side control circuit for carrying out control in accordance with a command from the control circuit 16; and 19 designates a buffer circuit that receives an output signal 115 of the inverter 15, and outputs the clock signal 116 from the output terminal Fout of the VCO 3.
FIG. 15 is a timing chart illustrating timing relationships between various portions of the VCO 3 in FIG. 14. In FIG. 15, reference numerals 111, 112, 113, 114 and 115 designate output signals of the inverters 11, 12, 13, 14 and 15, respectively, and 116 designates the clock signal output from the buffer circuit 19. For simplicity, the outputs of the inverters 11, 12, 13, 14 and 15 are assumed to have the same period, the same duty of 50% and the same rise and fall delay times.
The inverters 11-15 and the buffer circuit 19 each delay their output by .DELTA.t=t(n)-t(n-1) with respect to their input, where n is a given time, and the delay time .DELTA.t of the inverters 11-15 is determined by the ratio (period)/(the number of stages of the inverters).
In FIG. 14, receiving the voltage from the charge pump circuit 2 at its input terminal Vin, the VCO 3 controls the inverters 11-15 with the control circuits 16, 17 and 18 in response to the input voltage Vin, and produces from the inverter 15 the output signal 115. The output signal 115 has the same frequency as the reference clock signal CLK, and its period t1-t11 as illustrated in FIG. 15 is a period at which the PLL circuit 7 locks. The buffer circuit 19 inputs the output signal 115, and outputs the clock signal 116 from the output terminal Fout.
Thus, the conventional PLL circuit 7 fabricated by CMOS LSI technology comprises the VCO 3 including a ring oscillator consisting of multiple CMOS inverters connected in cascade. The multiple stage oscillator offers an advantage of being able to set the duty at 50% because the rising and falling edges of the output waveform are averaged. Conventionally, it is designed such that either the rising edge or the falling edge of the clock signal is used to operate the flip-flop circuits 6 in the LSI. Recently, however, an increasing number of logic circuit designs have come to use both the rising edge and falling edge to achieve high speed operation of the LSI.
With such an arrangement, the conventional PLL circuit 7 has a problem of likely causing the flip-flop circuits 6 to malfunction. The reason for this is that since all the flip-flop circuits 6 are controlled by the single clock signal 116 such that they transfer data at a high speed using both the rising and falling edges, a margin for time reduces between the data input to the flip-flop circuits 6 and the clock signal 116.
As a conventional technique relevant to the present invention, one disclosed in Japanese patent application laid-open No. 9-246920/1997 is known. It comprises, in a PLL circuit that includes a ring oscillator type VCO consisting of CMOS inverters, a selector for selectively outputting one of the outputs of the inverters, and supplies the output of the selector and the VCO output to a NAND circuit and a NOR circuit, respectively, to obtain besides the output signal of the VCO two outputs with different duties. It, however, cannot control the duties from the outside because it generates the outputs with different duties from the outputs of the inverters.
As another conventional technique relevant to the present invention, one disclosed in Japanese patent application laid-open No. 7-307665/1995 is known. It comprises, in a PLL that includes a ring oscillator consisting of CMOS inverters, digital loads that consist of capacitors or the like and are connected to the output portions of the inverters, controls the digital loads by detecting the operation frequency of its VCO to establish the operation frequency in a capture range of the PLL. It, however, cannot generate a plurality of signals with different duties, and the duties are uncontrollable from the outside.
As still another conventional technique relevant to the present invention, one disclosed in Japanese patent application laid-open No. 9-270680/1997 is known. It generates, in a ring oscillator type VCO consisting of a plurality of delay cells, signals which are delayed by every 1/2N of the oscillation period, and supplies them to first inputs of N XOR (Exclusive OR) circuits with their second inputs being supplied with the output of the VCO, thereby obtaining a frequency multiplied output. It, however, cannot output a plurality of signals with different frequencies, and the duty of the frequency multiplied output is uncontrollable from the outside.
As still another conventional technique relevant to the present invention, one disclosed in Japanese patent application laid-open No. 9-292930/1997 is known. It extracts various timing signals from appropriate nodes of inverters connected in cascade in a VCO, and supplies the timing signals to a logic circuit designated from the outside to obtain outputs with various timings and duties. Although it comprises delay circuits connected between nodes, the delay times of the delay circuits are uncontrollable from the outside.